| dc.contributor.author | Ahmed, Remon | |
| dc.contributor.author | Ahmed - Al- Nahid | |
| dc.contributor.author | Islam, Md. Jahurul | |
| dc.date.accessioned | 2023-05-08T05:13:33Z | |
| dc.date.available | 2023-05-08T05:13:33Z | |
| dc.date.issued | 2010-08-27 | |
| dc.identifier.uri | http://dspace.ewubd.edu:8080/handle/123456789/3980 | |
| dc.description | This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh. | en_US |
| dc.description.abstract | In this thesis we have represented the performance analysis of different types of nano-transistors such as single gate bulk MOSFET, double gate MOSFET, nanowire FET and CNTFET. Our observation is based on the ballistic transport at the top of the barrier model. The scattering effects on the current transport through the MOSFET are neglected in our observation. FETToy simulation tool was used to calculate the On - Current (Ion) and transconductance (gm) of different types of nano-transistors. We consider the change of insulator thickness (1ox) and initial source Fermi level (EF). Comparative discussion about the effects on Ion and gm in terms of changing MaS parameters are studied in this thesis. We observe that, the performance of nano-transistors improve with the switching of SG MOSFET to DG MOSFET, DG MOSFET to Si nanowire FET, Si nanowire FET to CNTFET. CNTFET has better On-Current (Ion) and transconductance (gm) over the other devices. On the other hand FETToy cannot properly model Subthreshold Swing (S) and Drain Induced Barrier Lowering (DIBL) in the top of the barrier model. | en_US |
| dc.language.iso | en_US | en_US |
| dc.publisher | East West University | en_US |
| dc.relation.ispartofseries | ;EEE00028 | |
| dc.subject | Dimensionality on the Performance of Nano-Transistors | en_US |
| dc.title | Effects of Reduced Dimensionality on the Performance of Nano-Transistors | en_US |
| dc.type | Thesis | en_US |