Abstract:
This thesis presents synthesis of the reversible comparator. The proposed circuits are
designed using only parity preserving Fredkin and Feynman double gates. Thus, these
circuits inherently turn into fault tolerant circuits. In addition, a lower bound on the
number of constant inputs and garbage outputs for the reversible fault tolerant
comparator has been proposed. It has been evidenced that the proposed circuit is
constructed with these optimal garbage outputs and constant inputs. Moreover, a design
algorithm for the generalized fault tolerant comparator has been presented. The
comparative results show that the proposed design performs much better and has
significantly better scalability than the existing approaches.
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh.