Abstract:
In this paper we proposed reversible synthesis for the several popular sequential
circuits such as shift register, binary adder and Multipliers. All the proposed
circuits are constructed with the parity preserving reversible gates. Thus, the
proposed circuits inherently become fault tolerant. In addition, several lower
bounds on the number of garbage outputs and constant inputs of the reversible fault
tolerant sequential circuits have been proposed. It has also been shown that the
proposed circuits are constructed with these optimal parameters. Moreover, the
generalized algorithms for the fault tolerant sequential circuits have been presented.
The performance study shows that the proposed fault tolerant circuits are much
faster than the existing reversible non-fault tolerant counterparts.
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh.