http://dspace.ewubd.edu:8080/handle/123456789/2032 Sun, 05 Apr 2026 23:48:49 GMT 2026-04-05T23:48:49Z http://dspace.ewubd.edu:8080/handle/123456789/2049 Strategies to Improve Power Delivery to CMOS Circuitry Using Localized Decoupling Mohaimen, Ophelia; Mustazir, Rezwana Habib; Sraboni, Laila Sharmin As current travels all the way from the power supply to the silicon, it sees the current path in each of the levels as resistive and inductive drops, thus voltage deteriorates. Power droop in the silicon is a major cause for system performance degradation. Higher frequency of operation and reduced power levels are limiting the timing and voltage budget, which is designed in circuits to account for system noise, which includes voltage drooping due to inductive losses. Novel techniques are evolved to compensate for these losses at all levels, starting from motherboard, package, socket and finally down to the silicon level. Due to lack of available space, design constraints and fabrication difficulties, decoupling at the die level is very limited. Though available decoupling techniques exist for the board, package and socket, yet their response time is slow and in some cases worthless. Here a proposal is made to provide for decoupling at the CMOS levels, right where the power is needed. This work merges the advanced DRAM technologies with that of CMOS to create decoupling in silicon without taking any extra rooms for it. Simulation of sub 100 run multi-metal layer circuit demonstrates the advantage of proposed localized decoupling. -ment This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh. Fri, 01 Jan 0012 00:00:00 GMT http://dspace.ewubd.edu:8080/handle/123456789/2049 0012-01-01T00:00:00Z http://dspace.ewubd.edu:8080/handle/123456789/2048 Signal Degradation in High Speed Systems Due To Chip Breakout Routing Constraints in Package Shadow Region Ghani, Md. Nahidul The High Speed Systems involves electrical performance of the wires and other packaging structures used to move signals about within an electronic product. In these early days of modern VLSI era, digital chip circuit design and layout were manual processes. The application of automatic synthesis techniques allowed designers to express their designs using high-level. Language and apply an automated design process to create very complex designs. Such performance is a matter of basic physics and as such has remained relatively unchanged since the inception of digital computing devices. As circuit shrinks in accordance with Moore's law, several signal integrity issues are becoming critical. Several of these issues are ringing, crosstalk, ",round bounce and power supply noise that can cause systems to fail particularly at high frequency. The socket breakout region requires important design consideration when signals are routed through it. In this region the trace width and trace spacing between them have to be decreased to maintain keep out region which are critical for manufacturing boards. However, decreasing trace space and width means increasing impedance. The high speed designer should maintain this thing very carefully as a matter of cost effective. This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh. Fri, 01 Jan 0012 00:00:00 GMT http://dspace.ewubd.edu:8080/handle/123456789/2048 0012-01-01T00:00:00Z http://dspace.ewubd.edu:8080/handle/123456789/2047 Via Effects on Signal Propagation in High Speed Transmission Lines Kashem, Saad Bin Abul With newer process and demand for increased system performance, clock speeds are getting faster and data transfer rates are increasing the acceleration of the system speed effects signal integrity. The reliable operation of system also becomes increasingly difficult To understand this problem extensive work on the matter is needed. The transmission lines are used in propagation systems to connect different devices. Data transmitted on from one device is carried by the transmission to another device [1]. This device can be a microprocessor or an application specific integrated circuit (ASIC). The data carrying capacity of the transmission lines is defined b its impedance. Transmission line's impedance not only depends on there own characteristics or parameters (material, thickness, dimension etc) but also on the characteristics of the features that exist in the environment surrounding them. The distribution of this impedance determines signal quality, which is best characterized by parameters such as noise, jitters, transmission delay or timing. It also embodies reflections, crosstalk and mismatches between drivers and receivers. This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh. Tue, 01 Jan 0009 00:00:00 GMT http://dspace.ewubd.edu:8080/handle/123456789/2047 0009-01-01T00:00:00Z